1. Field of the Invention
The present invention relates to a method for producing a semiconductor package and, particularly, to a method for producing a semiconductor package having fine circuit patterns arranged at a high density.
2. Description of the Related Art
A semiconductor package such as PPGA (Plastic Pin Grid Array) (which has a plurality of through holes into which respective pins are inserted); PBGA (Plastic Ball Grid Array) (which has a circuit pattern providing with land portions on which external connecting terminals, such as solder balls, are formed); or PLGA (Plastic Land Grid Array) (which has a circuit pattern providing with land portions which are served by themselves as external connecting terminals) is constructed by laminating a plurality of circuit boards with each other, and solder balls are bonded to a mounting surface as external terminals, wherein each of the circuit boards is composed of an electro-insulating substrate made of glass-epoxy resin, glass-polyimid resin, BT resin or others, on which an electro-conductive layer such as a copper foil is clad, as shown in FIG. 10.
A structure of the above semiconductor package 10 will be described with reference to FIG. 10.
An opening 14 is formed in each of the laminated resin boards 12 so that a cavity 16 is formed for accommodating a semiconductor element.
Inner circuit boards 20a and outer circuit boards 20b carrying circuit patterns 18 on both surfaces thereof are formed by etching the copper foil of the respective resin board.
Bonding portions of the circuit pattern 18 are formed in the vicinity of the periphery of the opening 14, for the connection of the circuit pattern to the semiconductor element by a wire bonding method. An area of the opening 14 in the inner circuit board 20a is determined so that, when a laminate is formed by laminating the circuit boards 20a with each other, a bonding portion is obtained in the respective circuit board 20a. Thus, when the inner circuit boards 20a and the outer circuit boards 20b are laminated with each other, the size of the cavity 16 in the respective circuit board 20a, 20b becomes larger as the position of the circuit board is higher in the cavity 16 of the laminated circuit board.
Each of the inner circuit boards 20a and the outer circuit boards 20b is adhered to the other circuit board via an adhesive sheet 22 (prepreg). Also, a resist (not shown) is coated on a surface of the circuit board 20a to flatten the surface and enhance the adhesivity between the circuit boards by the adhesive sheet 22. In this regard, if the property of the adhesive sheet 22 allows, the respective circuit boards 20a, 20b may be adhered to each other without the resist coating.
On the outer surface of the circuit board 20b, there are formed as a part of the circuit pattern 18 a land 26a for connecting an external terminal 24 (a bump in this case), a connector section 26b for the connection to a circuit element such as a capacitor or a resistor, or a conductor 26c for mounting a heat-radiation plate made of a metallic plate. A protective coating 28 such as a solder resist is provided on the outer surface of the circuit board 20b, while taking a care so that the land 26a, the connector section 26b and the conductor are solely exposed. Also, the bonding portions are electrically conductive to the lands 26a, the connector section 26b, or the like, via through-holes 29.
The external terminals 24 are mounted to the land 26a, and a circuit element and a heat-radiating plate 30 are mounted to the connector section 26b and the conductor 26c.
However, the above-mentioned prior art method for producing a semiconductor package has the following problems:
In the prior art, the through-hole 29 is generally formed in such a manner that a laminate is prepared by laminating the inner circuit boards 20a and the outer circuit boards 20b with each other via the adhesive sheets 22, and a bore is provided through the laminate, wherein electroless plating and an electroplating of copper are applied to the inner wall of the bore to provide a conductor for connecting circuit patterns in the inner circuit boards 20a with each other and finally a nickel plating and a gold plating are applied to the conductor.
Although there is a case wherein the user demands in the product specification that, even after being subjected to a predetermined heat-shock test, the semiconductor package should be free from short-circuit accidents in an electric test for the through-hole 29 and from a ply separation between circuit patterns formed on the respective circuit boards 20a, 20b, the through-hole 29 having a conductor formed of a plated nickel coating and a plated gold coating does not satisfy such a demand, but is damaged by about 100 cycles of a heat-shock test wherein a temperature varies in a range from -55.degree. C. to 125.degree. C., while the product specification demands 1000 cycles.
Accordingly, in a PPGA type semiconductor package, a pin is inserted into a through-hole and soldered thereto although not shown, and in a PLGA type semiconductor package, a solder is filled in a through-hole so that the demand for the heat-shock test is satisfied. However, the pin-insertion method requires a complicated process, while the solder-filling method has an environmental contamination problem due to lead contained in the solder.
To improve the resistance to heat-shock of the through-hole without using the pin-insertion or solder-filling method, it has been found that if two plated nickel coatings are applied onto the through-hole conductor, resistance to cracking and/or debonding is improved to enhance the reliability.
However, if a nickel-plating is merely applied twice to the laminate, the nickel-plating is also applied to the bonding portion of the circuit pattern 18 in the inner circuit board 20a in the cavity 16. This results in a short-circuit between the circuit patterns 18 in the inner circuit boards 20a which are exposed in the cavity 16, because the bonding portions thereof becomes thicker and wider due to the double plated nickel coatings, especially when the number of pins of the semiconductor element to be mounted into the cavity 16 increases very much and the bonding portions of the circuit patterns 18 in the inner circuit boards 20a are fine and dense. Similarly, when an electroless plating and an electro plating of copper are applied to the inner wall of a bore provided in the laminate formed by laminating the inner circuit boards 20a and the outer circuit boards 20b via the adhesive sheets 22, for the purpose of forming the through-hole, the plated metal is deposited on the bonding portion of the circuit pattern 18 in the inner circuit board 20a in the cavity 16 to result in the short-circuit between the bonding portions of the circuit patterns 16.
Accordingly, when the electroless plating and the electro-plating of copper are applied to the through-hole or the nickel plating is applied, it is necessary to mask the interior of the cavity 16 and remove the mask after the plating, which lowers the workability.